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WM9710
AC'97 Audio CODEC and Mixer with Integrated Headphone Driver
DESCRIPTION
The WM9710 is a high-quality stereo audio codec with an integrated headphone driver. The device is compliant with the Intel AC'97 Rev 2.2 specification. It performs full-duplex 18-bit codec functions and supports variable sample rates from 8kHz to 48kHz with high signal to noise ratio. Analogue mixers are included to mix external analogue signals into the playback or record path. The WM9710 allows designers to easily integrate phone functions with other audio functions such as MP3 playback and voice recording. Mono inputs and outputs are provided to connect to an external voice codec. The on-chip headphone driver can distinguish between a stereo headphone and mono headset, and route the signals accordingly. Optional AC'97 features include 3D sound enhancement, 2 primary/secondary mode operation and S/PDIF or I S output. The 5-pin bi-directional AC-Link interface transfers control data, DAC and ADC words to and from the AC'97 controller. The WM9710 is fully operable on 3V or 5V or mixed 3/5V supplies, and is packaged in a leadless, chip scale QFN package with 7mm body size or 48-pin TQFP package.
FEATURES
* * * * * * * * * * * AC'97 rev2.2 compliant, 18-bit stereo codec Integrated headphone driver Automatic headset detection and switching (for stereo headphones / mono phone headsets) Separately mixed mono output for phone TX path (also includes headphone buffer for mono earpiece) Multiple channel input mixer Mono inputs for phone RX and PCBEEP signals On-chip sample rate conversion, supports rates from 8kHz to 48kHz. DAC and ADC rates are fully independent. Optional S/PDIF or I2S digital audio output 3V to 5V operation Each circuit block can be separately powered on or off Leadless 7mm x 7mm x 0.9mm QFN or 48-pin TQFP package
APPLICATIONS
* * Personal Digital Assistants and `Smartphones' WinCE systems
BLOCK DIAGRAM
DGND1 DVDD1 DGND2 DVDD2 CX3D1 CX3D2
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WM9710
LINEINVOL (Reg 10h) CDVOL (Reg 12h) MICVOL (Reg 0Eh) ADCNDAC (Reg 5Ch) MUX HPND (Reg 5Ch) M U X MIXVOL (Reg 72h) MPM (Reg 5Ah) HPVOL (Reg 04h)
16 / 32Ohm headphone HPOUTL HPOUTR HPGND
3D
LINEINL LINEINR CDL CDGND CDR MIC2 MIC1
M U X
MIC BOOST MIC SELECT (Reg 0Eh) (Reg 20h) M 0/20 U dB X M U X headset autodetect HPOUTL PHONE
RECORD GAIN (Reg 1Ch)
ADC L
DIGITAL FILTERS MODULATION
DAC L
POP (Reg 20h)
MASTER VOL (Reg 02h)
RECORD SELECT (Reg 1Ah)
ADC R
VARIABLE RATE AUDIO
DAC R
DACVOL (Reg 18h) MIX (Reg 20h) (Reg 0Ah) (Reg 0Ch) M U X M U X MONO VOL (Reg 06h) PSEL (Reg 5Ch)
LINEOUTL LINEOUTR
MONO_OUT (TX)
VREFOUT
VREF
CONTROL LOGIC
AC'97 INTERFACE
CLOCK OSC
PHIZ (Reg 78h)
XTLOUT
HSDET EAPD PWRUP/LRC SPEN/I2S SPDIF CID0
VREF
XTLIN
PCBEEP
BITCLK SYNC SDATAIN SDATAOUT RESETB
24.576MHz
WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com
Production Data, December 2003, Rev 4.0
Copyright 2003 Wolfson Microelectronics plc
PHONE (RX)
AGND
AVDD
CAP2
WM9710
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TABLE OF CONTENTS DESCRIPTION ............................................................................................................1 FEATURES..................................................................................................................1 APPLICATIONS ..........................................................................................................1 BLOCK DIAGRAM ......................................................................................................1 TABLE OF CONTENTS ..............................................................................................2 ORDERING INFORMATION .......................................................................................3 ABSOLUTE MAXIMUM RATINGS..............................................................................3 RECOMMENDED OPERATING CONDITIONS ..........................................................4 PIN CONFIGURATION................................................................................................5 PIN DESCRIPTION .....................................................................................................6 ELECTRICAL CHARACTERISTICS ...........................................................................7 POWER CONSUMPTION ...........................................................................................9 DETAILED TIMING DIAGRAMS ...............................................................................11
AC-LINK LOW POWER MODE .........................................................................................11 COLD RESET....................................................................................................................11 WARM RESET ..................................................................................................................12 CLOCK SPECIFICATIONS ...............................................................................................12 DATA SETUP AND HOLD (50PF EXTERNAL LOAD).......................................................13 SIGNAL RISE AND FALL TIMES ......................................................................................13
DEVICE DESCRIPTION............................................................................................14
INTRODUCTION ...............................................................................................................14 AC'97 FEATURES.............................................................................................................14 NON - AC'97 FEATURES..................................................................................................14 3-D STEREO ENHANCEMENT.........................................................................................15 VARIABLE SAMPLE RATE SUPPORT .............................................................................15 2 SPDIF OR I S DIGITAL AUDIO DATA OUTPUT...............................................................16 PRIMARY/SECONDARY ID SUPPORT ............................................................................16 HEADPHONE DRIVE AND HEADSET AUTODETECT .....................................................17 DATA SLOT MAPPING .....................................................................................................18 AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL ......................................................18 REGISTER 28H - EXTENDED AUDIO ID.........................................................................24 REGISTER 2AH - EXTENDED AUDIO STATUS AND CONTROL REGISTER ................24 REGISTER 2CH AND 32H - AUDIO SAMPLE RATE CONTROL REGISTERS................25 REGISTERS 3AH - SPDIF CONTROL REGISTER ..........................................................25 VENDOR SPECIFIC REGISTERS (INDEX 5AH - 7AH) ....................................................25
SERIAL INTERFACE REGISTER MAP ....................................................................28 PACKAGE DIMENSIONS - TQFP............................................................................30 PACKAGE DIMENSIONS - QFN..............................................................................31 IMPORTANT NOTICE ...............................................................................................32
ADDRESS: ........................................................................................................................32
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ORDERING INFORMATION
DEVICE XWM9710EFT/V WM9710SEFT/V XWM9710EFT/RV WM9710SEFT/RV TEMP. RANGE -25 to 85oC -25 to 85 C -25 to 85oC -25 to 85oC
o
PACKAGE 48-pin TQFP 48-pin TQFP (lead free) 48-pin TQFP (tape and reel) 48-pin TQFP (lead free, tape and reel)
MOISTURE SENSITIVITY LEVEL MSL1 MSL1 MSL1 MSL1
DEVICE XWM9710EFL/V WM9710SEFL/V XWM9710EFL/RV WM9710SEFL/RV Note: Reel quantity = 2,200
TEMP. RANGE -25 to 85oC -25 to 85 C -25 to 85oC -25 to 85oC
o
PACKAGE 48-pin QFN 48-pin QFN (lead free) 48-pin QFN (tape and reel) 48-pin QFN (lead free, tape and reel)
MOISTURE SENSITIVITY LEVEL MSL3 MSL3 MSL3 MSL3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. Note: The TQFP version is classified as MSL1 and does not require to be drybagged but will be supplied as such, labelled as MSL1. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) MIN -0.3V -0.3V DVSS -0.3V AVDD -0.3V -25oC -65oC MAX +7V +7V DVDD +0.3V AVDD +0.3V +85oC +150oC +240oC +183oC
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RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Digital ground Analogue ground Difference AGND to DGND - Note 1 Difference AVDD to DVDD - Note 2 Note: 1. AGND is normally the same as DGND and HPGND 2. AVDD should be greater than or equal to DVDD SYMBOL DVDD1, DVDD2 AVDD DGND1, DGND2 AGND, HPGND -0.3 -0.3 TEST CONDITIONS MIN 2.7 2.7 0 0 0 +0.3 5.5 TYP MAX 5.5 5.5 UNIT V V V V V V
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PIN CONFIGURATION
PWRUP / LRC MONO_OUT 37 36 35 34 33 32 LINEOUTR LINEOUTL CX3D2 CX3D1 CAP2 DNC DNC DNC VREFOUT VREF DNC DNC 31 30 29 28 27 26 25 13 PHONE 14 DNC 15 DNC 16 DNC 17 DNC 18 CDL 19 CDGND 20 CDR 21 MIC1 22 MIC2 23 LINEINL
37 36 35 34 33 32 LINEOUTR LINEOUTL CX3D2 CX3D1 CAP2 DNC DNC DNC VREFOUT VREF DNC DNC MONOOUT 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 LINEINR
SPEN / I2S
HPOUTR
HPOUTL 39
HPGND
HSDET
SPDIF
AGND
48 DVDD1 XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DVDD2 SYNC RESETB PCBEEP 1 2 3 4 5 6 7 8 9 10 11 12
47
46
45
44
43
42
41
40
38
WM9710 QFN
AVDD
EAPD
CID0
24 LINEINR
Figure 1 QFN Pinout
PWRUP/LRC
SPEN/I2S
HPOUTR
HPOUTL 39 MIC2
HPGND
AGND2
EAPD
48 DVDD1 XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DVDD2 SYNC RESETB PCBEEP 1 2 3 4 5 6 7 8 9 10 11 12
47
46
45
44
43
42
41
40
38
WM9710 WM9710 TQFP QFN
DNC
CDGND
DNC
DNC
PHONE
CDR
CDL
Figure 2 TQFP Pinout
LINEINL
MIC1
DNC
AVDD2
HSDET
SPDIF
CID0
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PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 48 PIN TQFP OR 48 QFN DVDD1 XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DVDD2 SYNC RESETB PCBEEP PHONE DNC DNC DNC DNC CDL CDGND CDR MIC1 MIC2 LINEINL LINEINR DNC DNC VREF VREFOUT DNC DNC DNC CAP2 CX3D1 CX3D2 LINEOUTL LINEOUTR MONOOUT AVDD HPOUTL HPGND HPOUTR AGND PWRUP/LRC SPEN/I S CID0 HSDET EAPD SPDIF
2
TYPE Supply Digital input Digital output Supply Digital input Digital I/O Supply Digital output Supply Digital input Digital input Analogue input Analogue input Do Not Connect Do Not Connect Do Not Connect Do Not Connect Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Analogue input Do Not Connect Do Not Connect Analogue output Analogue output Do Not Connect Do Not Connect Do Not Connect Analogue I/O Analogue output Analogue input Analogue output Analogue output Analogue output Supply Analogue output Supply Analogue output Supply Digital I/O Digital I/O Digital input Digital output Digital output Digital output Digital supply
DESCRIPTION
Clock crystal connection or clock input (if XTAL not used) Clock crystal connection Digital ground Serial data input (AC-Link signal) Serial interface clock (AC-Link signal) Digital ground Serial data output (AC-Link signal) Digital supply Serial interface sync pulse (AC-Link signal) Reset input (active low, resets registers) PCBEEP input (mono input to mixer) Phone RX input (mono input to mixer) Leave this pin floating Leave this pin floating Leave this pin floating Leave this pin floating CD Left (stereo input to mixer) CD input common mode reference (ground) CD Right (stereo input to mixer) Microphone input 1 - also HSET detect input Microphone input 2 Line-in Left (stereo mixer input) Line-in Right (stereo mixer input) Leave this pin floating Leave this pin floating Internal reference (buffered CAP2) Microphone bias voltage (buffered CAP2) Leave this pin floating Leave this pin floating Leave this pin floating Reference input/output; pulls to AVDD/2 if not overdriven Output pin for 3D enhancement function Input pin for 3D enhancement function Line-out Left Line-out Right Mono output (Phone TX or mono earpiece) Analogue supply Headphone output Left (or headset mic input if headset detect function is enabled) Headphone ground Headphone output Right Analogue ground Power-up control (or LRCLK signal for I2S output) SPDIF hardware enable pin and I2S data output Primary/Secondary codec select (internal pull-up) Hi = Primary Headset detect signal External amplifier powerdown (or general purpose control output) S/PDIF output
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ELECTRICAL CHARACTERISTICS
Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, 48kHz audio sampling, TA = 25oC, unless otherwise stated. PARAMETER Digital Logic Levels (DVDD = 3.3V) Input LOW level Input HIGH level Output LOW Output HIGH Input level Output level to LINEOUT L,R Output level to HPOUT L, HPOUTR and MONOOUT Reference Levels Reference input/output CAP2 impedance Mixer reference MIC reference MIDBUFF current source (pins VREF and VREFOUT) MIDBUFF current sink (pins VREF and VREFOUT) AUDIO DAC to Line-out (10k load) SNR A-weighted (Note 2) Full scale output voltage Total Harmonic Distortion + Noise PSRR AUDIO ADC ADC input for full scale output Signal to Noise Ratio A-weighted (Note 2) Total Harmonic Distortion+Noise Power Supply Rejection Ratio Digital Filter Characteristics Frequency response Transition band Stop band Stop band attenuation ADC DAC 20 19,200 28,800 -74 -40 19,200 28,800 Hz Hz Hz dB SNR THD+N PSRR -6dBfs input 20 to 20kHz, without supply decoupling VREF = 1.65V 80 0.7 86 -79 -40 -72 Vrms dBfs dB dB THD+N VREF = 1.65V -3dBfs input 20 to 20kHz, without supply decoupling 85 91 0.7 -84 0.006 -40 -74 0.02 dB Vrms dB % dB VREF VREFOUT AVDD = 3.3V AVDD = 3.3V 5 -5 CAP2 0.47 AVDD 0.50 AVDD 75 Buffered CAP2 Buffered CAP2 10 -10 0.53 AVDD V k V V mA mA VIL VIH VOL VOH I Load = 2mA I Load = -2mA Minimum input impedance = 10k Into 10k load Into 16 load 0.90 x DVDD AGND -100mV AGND +300mV AGND +300mV AVDD +100mV AVDD -300mV AVDD -300mV DGND - 0.3 2.2 0.8 DVDD + 0.3 0.10 x DVDD V V V V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Audio I/O Levels (Input Signals on any audio inputs, Outputs on LINEOUT L, R and MONO and HPOUT L,R)
Near rail to rail Near rail to rail
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Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, 48kHz audio sampling, TA = 25oC, unless otherwise stated. PARAMETER Maximum input voltage Maximum output voltage Signal to Noise Ratio A-weighted (Note 2) Total Harmonic Distortion + Noise -1dBfs input SNR THD+N on LINEOUT CD inputs Other inputs CD and LINE inputs PHONE input MIC1 input MIC2 input PCBEEP input Input impedance (CD inputs) Input impedance (other mixer inputs) At any gain 10 50 10 55 90 82 SYMBOL TEST CONDITIONS MIN AGND TYP 0.7 0.7 92 93 -87 0.0044 -82 0.008 -82 0.008 -90 0.003 -78 0.013 15 20 100 20 100 -40 -77 0.014 -71 0.028 -71 0.028 -71 0.028 -67 0.045 MAX AVDD
Production Data
UNIT Vrms Vrms dB dB %
Mixer Inputs to Line-out (10k load)
k k k k k dB
At max gain At 0db gain Input impedance MIC inputs At max gain At 0db gain Power Supply Rejection Ratio PSRR 20 to 20kHz, without supply decoupling Headphone Buffer (pins HPOUTL, HPOUR and MONOOUT) Maximum output voltage Max Output Power (Note 1) SNR (Note 2) Total Harmonic Distortion + Noise THD+N PO RL = 32 RL = 16 A-weighted 1kHz, RL = 32 @ PO = 10mW rms 1kHz, RL = 32@ PO = 20mW rms 1kHz, RL = 16 @ PO = 10mW rms 1kHz, RL = 16@ PO = 20mW rms 20 to 20kHz, without supply decoupling
85
0.7 30 40 92 -80 0.01 -77 0.014 -76dB 0.016 -75dB 0.018 -40
Vrms mW mW dB dB % dB % dB % dB % dB
Power Supply Rejection Ratio Clocks Crystal clock BITCLK frequency SYNC frequency
PSRR
24.576 12.288 48.0
MHz MHz KHz
Note: 1. Harmonic distortion on the headphone output decreases with output power - see Figure 3. 2. SNR is the ratio of 0dB signal amplitude to noise floor with no signal present (all 0s input code to DACs). 3. ADC sampling capacitance allows the user to calculate the minimum external capacitance required for a stable ADC value.
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-100 -90 -80 THD+Noise (dB) -70 -60 -50 -40 Output Power (mW) -30 0 5 10 15 20 25 30
Figure 3 Distortion Versus Power on Headphone Outputs, using 32 Load and AVDD = HPVDD = 3.3V
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POWER CONSUMPTION
DIGITISER PD REG 78H (PRP) RECORD MUX
MODE DESCRIPTION CURRENT CONSUMPTION
EAPD
PR0
PR1
PR2
PR3
PR5
PR4
PR6
AVDD (mA
DVDD (mA)
TOTAL POWER (mW)
Record and Playback Mic Record (note 1) Other Input Record Other Input Record PR6 Other Input Record PR6 and PR2 Other Input Record PR6 and PR3 Playback Only Low Power Playback (note 2) Playback Only Playback Only PR6 Playback Only PR6 and PR2 Playback Only PR6 and PR3 Record Only Mic Record (note 1) Other Input Record Other Input Record PR6 Other Input Record PR6 and PR2 Other Input Record PR6 and PR3 Power Down Power Down (note 3) Pen Digitiser Pen Digitiser (Note 4) 1 1 1 1 0 1 1 X 11 XXXL XXXR 0.1 3.6 12.2 1 1 1 1 1 1 1 X 00 XXXL XXXR 0.0001 0.002 0.007 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 X X X X X 00 00 00 00 00 000L 000R 100L 100R 100L 100R 100L 100R 100L 100R 12.9 15.8 14.3 7.2 0.3 13.3 13.3 11.3 13.3 12.9 86.5 96 84.5 67.7 43.6 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 X X X X X 00 00 00 00 00 001L 001R 001L 001R 001L 001R 001L 001R 001L 001R 5.5 11.1 9.7 4.0 0.4 11.5 11.5 11.5 11.5 11.5 56.1 74.6 70 51.2 39.3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 X X X X X 00 00 00 00 00 000L 000R 001L 001R 001L 001R 001L 001R 001L 001R 14.8 17.7 16.3 10.7 0.5 14.3 14.3 14.3 14.3 14.1 96 105.6 101 82.5 48.2
Notes: 1. When the ADC input mux is set to mic input to BOTH ADC channels, (SR2-0 and SL2-0 both set to `0'), one ADC is shared between both channels and the other is powered off to save current. The same digital data is output to both slots. 2. The POP bit (reg 20h) also needs to be set for this mode. 3. These values are recorded with no external clocks applied to the WM9705. 4. Pen active duty cycle is approximately 10%. Average analogue current consumption is approximately 10% of stated figure.
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DETAILED TIMING DIAGRAMS
Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, AGND = 0V ..............TA = 0oC to +70oC, unless otherwise stated. All measurements are taken at 10% to 90% DVDD, unless otherwise stated. All the following timing information is guaranteed, not tested.
AC-LINK LOW POWER MODE
SLOT 1 SYNC
SLOT 2
BITCLK
SDATAOUT
WRITE TO 0X20
DATA PR4
DON'T CARE
tS2_PDOWN SDATAIN
Figure 4 AC-Link Powerdown Timing PARAMETER End of slot 2 to BITCLK SDATAIN low SYMBOL tS2_PDOWN MIN TYP MAX 1.0 UNIT
s
COLD RESET
tRST_LOW RESETB tRST2CLK
BITCLK
Figure 5 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or Wolfson applications note WAN104 for more details. PARAMETER RESETB active low pulse width RESETB inactive to BITCLK startup delay SYMBOL tRST_LOW tRST2CLK MIN 1.0 162.8 TYP MAX UNIT
s
ns
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tSYNC_HIGH SYNC tSYNC2CLK
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BITCLK
Figure 6 Warm Reset Timing PARAMETER SYNC active high pulse width SYNC inactive to BITCLK startup delay SYMBOL tSYNC_HIGH tSYNC2CLK 162.4 MIN TYP 1.3 MAX UNIT
s
ns
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC tSYNC_PERIOD
Figure 7 Clock Specifications (50pF External Load) PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (Note 1) BITCLK low pulse width (Note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Note: Worst case duty cycle restricted to 45/55. tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 36 36 40.7 40.7 48.0 20.8 1.3 19.5 tCLK_PERIOD SYMBOL MIN TYP 12.288 81.4 750 45 45 MAX UNIT MHz ns ps ns ns kHz
s s s
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WM9710 DATA SETUP AND HOLD (50PF EXTERNAL LOAD)
tSETUP BITCLK tHOLD SDATAIN SDATAOUT tSETUP SYNC tHOLD
Production Data
Figure 8 Data Setup and Hold (50pF External Load) Note: Setup and hold time parameters for SDATAIN are with respect to AC'97 Controller. PARAMETER Setup to falling edge of BITCLK Hold from falling edge of BITCLK SYMBOL tSETUP tHOLD MIN 10 10 TYP MAX UNIT ns ns
SIGNAL RISE AND FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Figure 9 Signal Rise and Fall Times (50pF External Load)
PARAMETER BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time
SYMBOL triseCLK tfallCLK triseSYNC tfallSYNC triseDIN tfallDIN triseDOUT tfallDOUT
MIN 2 2 2 2 2 2 2 2
TYP
MAX 6 6 6 6 6 6 6 6
UNIT ns ns ns ns ns ns ns ns
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DEVICE DESCRIPTION
INTRODUCTION
This specification describes the WM9710 audio codec, which is designed to be software and hardware compatible with the Intel AC'97 rev2.2 component specification. The device is a derivative of the basic AC'97 codec. Variable Rate Audio (VRA) is supported at rates defined in the Intel rev2.1 or rev2.2 specification, and a SPDIF output port is provided which may optionally be used to output the PCM DAC information to external processors. WM9710 offers the following features: Stereo Audio Codec with Intel specified VRA support of different audio sample rates Optional SPDIF and I2S audio outputs (SPDIF output may be hardware enabled so needing no driver support) Headphone drive capability and optional auto detection of headset or headphone plug in It is highly recommended that the Intel AC'97 rev2.2 specification be studied in parallel with this document: This specification can be downloaded from the Intel web site. The WM9710 is fully operable on 3V or 5V or mixed 3/5V supplies, and is packaged in the industry standard 48pin TQFP package with 7mm body size.
AC'97 FEATURES
WM9710 implements the base set of AC'97 rev2.2 features, plus several enhancements: All rev2.2 specified variable audio sample rates supported 3-D stereo enhancement feature. Headphone support on HPOUT outputs (pins 39,41) Primary/secondary codec operation by pin programming of CID0 pin SPDIF audio output with rev2.2 compliant control set.
NON - AC'97 FEATURES
In addition to the AC'97 features offered, WM9710 also supports: Headphone drive capability on MONO output, with extra signal routing switch PSEL, allowing PHONE input to be routed to MONO output Extra switch HPND after the mixer allowing MIX without DAC signal to be output to headphone outputs, and so allowing DAC with no MIX to be output to LINE outputs. I2S audio output capability, in addition to SPDIF output, allowing support of an extra external audio DAC for multi-channel solutions. SPDIF output may be hardware enabled. Option to route the stereo audio ADC output to the SPDIF and/or I2S digital outputs Auto-detect of headphones or headset plugged into the HPOUT headphone outputs, with internal routing of microphone signal from the headphone pin to the MIC1 input. MPM switch allowing mix of DAC + mixer output onto MONOUT and independent mix of DAC + PHONE and/or PCBEEP onto LINEOUT or HPOUT. Reset powerdown override - holding PWRUP/LRC (PIN 43) high in reset overrides the PR bits forcing the WM9710 into a low power mode.
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WM9710 3-D STEREO ENHANCEMENT
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This device contains a stereo enhancement circuit, designed to optimise the listening experience when the device is used in a typical PC operating environment. That is, with a pair of speakers placed either side of the monitor with little spatial separation. This circuit creates a difference signal by differencing left and right channel playback data, then filters this difference signal using lowpass and highpass filters whose time constants are set using external capacitors connected to the CX3D pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass poles at about 100Hz and 1kHz respectively. This frequency band corresponds to the range over which the ear is most sensitive to directional effects. The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to Register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h is optimum. The user interface would most typically use a slider type of control to allow the user to adjust the level of enhancement to suit the program material. Bit D13 3D in Register 20h is the overall 3D enable bit. The Reset Register 00h reads back the value 11000 in bits D14 to D10. This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement. Note that the external capacitors setting the filtering poles applied to the difference signal may be adjusted in value, or even replaced with a direct connection between the pins. If such adjustments are made, then the amount of difference signal fed back into the main signal paths may be significant, and can cause large signals which may limit, distort, or overdrive signal paths or speakers. Adjust these values with care, to select the preferred acoustic effect. There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied (if the signals are in phase and of the same amplitude). Signals from the PCM DAC channels can have stereo enhancement applied. It can also be bypassed if desired. This function is enabled by setting the bit POP in Register 20h.
VARIABLE SAMPLE RATE SUPPORT
The DACs and ADCs on this device support all the recommended sample rates specified in the Intel AC'97 rev2.1 & rev2.2 specifications for audio rates. The default rate is 48kHz. If alternative rates are selected and variable rate audio is enabled (Register 2Ah, bit 0), the AC'97 interface continues to run at 48k words per second, but data is transferred across the link in bursts such that the net sample rate selected is achieved. It is up to the AC'97 Revision 2.1/2 compliant controller to ensure that data is supplied to the AC link, and received from the AC link, at the appropriate rate. Variable rates are selected by writing to registers 2Ch (DAC) and 32h (ADC). ADC and DAC rates may be set independently, with left and right channels always at the same rate. The device supports on demand sampling. That is, when the DAC signal processing circuits need another sample, a sample request is sent to the controller which must respond with a data sample in the next frame it sends. For example, if a rate of 24kHz is selected, on average the device will request a sample from the controller every other frame, for each of the stereo DACs. Note that if an unsupported rate is written to one of the rate registers, the rate will default to the nearest rate supported. The Register will then respond, when interrogated, with the supported rate the device has defaulted to. The WM9710 clocks will scale automatically dependent upon the MCLK frequency, where MCLK is not equal to 24.576MHz. With a 24MHz clock the BCLK frequency expected will be 12MHz and the sampling frequency (SYNC0 expected is BCLK/256 = 46.875kHz. AUDIO SAMPLE RATE 8000 11025 16000 22050 32000 44100 48000 CONTROL VALUE D15-D0 1F40 2B11 3E80 5622 7D000 AC44 BB80
Table 1 Variable Sample Rates Supported
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WM9710 SPDIF OR I S DIGITAL AUDIO DATA OUTPUT
2
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The WM9710 SPDIF output may be enabled in hardware by holding pin 44 (SPEN) high when RESETB is taken high, or by writing to the SPDIF control bit in register 2Ah. If SPDIF pin 48 is pulled high at start-up by a weak pull-up (e.g. 100k), then SPDIF capability bit in register 28h is set to `0', i.e. no SPDIF capability. This allows for stuffing options, so that when SPDIF external components are not provided, the driver will see `no SPDIF capability' and `grey out' the relevant boxes in the control panel. Additionally the digital audio may be output in I2S format using pin 44 (SPEN) as the data output, and outputting a frame clock or LRCLK onto pin 43. The data is clocked onto pin 44 using the regular BITCLK at 256fs, which would also then be used as the MCLK if the data is taken to an external DAC. Operation in this mode is selected by setting bit I2S in register 5Ch. A 64fs bitclk is also available and can be output on SPDIF by setting bit I2S64 in register 74h. Note that I2S operation is only supported for 48kHz operation. Hardware selection of SPDIF operation by pulling pin SPEN `hi' is compatible with I2S operation, provided a weak pull-up (circa 100k) was used to 2 2 hold SPEN high at start-up. The SPEN pin becomes I S data output pin when I S is enabled, and the weak pull-up on this pin is overdriven. For both SPDIF and I2S modes the data that is output may be sent from the WM9710 via the AC link in the same slots as normal DAC data or may be sent in different slots. The output slots that contain the SPDIF/I2S data are selected by bits SPSA[1:0] in register 2Ah. WM9710 is compliant with AC'97 rev2.2 specification with regard to slot mapping; therefore the default mode of operation is to output SPDIF or I2S data from the next data slots available after the audio data slots currently in use. Alternatively if required, data may be mapped from any of the available slots by selection using SPSA bits. The following table shows the default slot mapping for audio DACs and SPDIF/I2S data: (further details in the register description section later).
SPEN STATE AT START-UP `lo' (rev2.2 compliant) `lo' (rev2.2 compliant) `hi' (WM proprietary) `hi' (WM proprietary)
CODEC ID (PIN 45 STRAPPING) `hi' = ID = 0 = primary `lo' = ID = 1 = secondary `hi' = ID = 0 = primary `lo' = ID = 1 = secondary
AUDIO DAC SLOT DEFAULT Slots 3 & 4 - front channels Slots 7 & 8 - surround Slots 3 & 4 - front channels Slots 7 & 8 - surround
SPDIF OR I S DATASLOT DEFAULT Slots 7 & 8 Slots 6 & 9 Slots 3 & 4 Slots 3 & 4
2
Table 2 DAC and SPDIF Slot Mapping Defaults However, an exception to the rev2.2 mapping table is made when SPDIF operation is enabled using the SPEN hardware enable pin (being held high at start-up): in this case SPDIF data is immediately output from the DAC primary slots 3 & 4. This allows for driver-less SPDIF operation, where the SPDIF or I2S output is simply the data contained in the main audio DAC channels. Channel status and control bits output along with the SPDIF data are as set in the SPDIF control register 3Ah. If required SPDIF data channel slot mapping may be then changed by setting SPSA bits as required. See tables 18, 19 and 20 for further details. A mode is provided where the output from the ADC is sent out as the SPDIF or I2S data as above, rather than the data sent to the DACs over the AC link. This mode is enabled by setting bit ADCO in register 5Ch. ADC data continues to be sent via the AC link to the controller as normal. WM9710 supports SPDIF and I2S data only at the default 48kHz frame rate. Writing to SPSR bits in register 3Ah any value other than the default 48kHz rate will result in a fail to write, with the 48kHz value being returned on subsequent reads of these values.
PRIMARY/SECONDARY ID SUPPORT
WM9710 supports operation as either a primary or a secondary codec. Configuration of the device as either a primary or as a secondary, is selected by tying the CID0 pin 45 on the package. Fundamentally, a device identified as a primary (ID = 0, CID0 = `hi') produces BITCLK as an output, whereas a secondary (any other ID) must be provided with BITCLK as an input. This has the obvious implication that if the primary device on an AC link is disabled, the secondary devices cannot function. The AC'97 Revision 2.2 specification defines that the CID0 pin has inverting sense, and are provided with internal weak pull ups. Therefore, if no connections are made to the CID0 pin, then the pin pull hi and an ID = 0 is selected, i.e. primary. External connect to ground (with pull-down from 0 to 10k) will select codec ID = `1'.
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PIN 45 CID0 NC or pull-up Ground ID SELECTED 0 1 PRIMARY OR SECONDARY Primary Secondary BITCLK Output Input
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Table 3 Codec ID Selection
HEADPHONE DRIVE AND HEADSET AUTODETECT
Headphone drive capability is provided on HPOUT (pins 39 and 41) and on MONOOUT (pin 37). Headphones of impedance typically from 16 upwards may be connected to these pins. AC coupling with an appropriately sized capacitor is recommended for removal of the mid-rail DC pedestal present on these outputs. AC'97 rev2.2 specification recommends 32 headphones; if a headphone is connected for use as a headset, where the stereo ear-pieces are driven in parallel, then each capsule must be of minimum 32 impedance. In many applications it is desirable to be able to connect either a stereo headphone to the headphone output pins, or a mono headset, comprising ear-piece(s) and a microphone. The microphone signal is sent via the tip connected wire of the typical 3-wire jack. In this event it is desirable to be able to auto-detect the connection of either the headphone or the headset (with microphone). The main characteristic of the headset and microphone compared to the headphone is that the microphone impedance is typically much higher than the headphone capsule (assuming a typical moving coil headphone). Because of this it is possible to connect a weak pull-up to the tip connection of the headphone jack. When a headphone is connected the low impedance to ground of the headset pulls down the DC level to near ground. If a headset with microphone is plugged in, the high impedance of the microphone does not pull down the DC level on the tip connection, the DC on this pin now rising to near positive supply. This change in DC level is detected, so allowing detection of change from headphone to microphone, (or nothing plugged in of course). When this event is detected, the headphone amplifier that drives the tip connection is turned off, and the signal on this pin is routed instead to the MIC1 input as a microphone input. This auto-detect comparator is enabled by setting bit HSCMP. The pull-up current is enabled by setting bit MPUEN in register 5Ch and also toggles the interrupt signal on the HSDET pin. When bit HSDT is set the mic1 input is connected to a comparator with a threshold set at mid-rail. When the comparator output is low, then the headphone driver is enabled. When the comparator output goes high (that is the pull-up current multiplied by the external impedance to ground on the mic1 pin is greater than mid-rail), the headphone amplifier is turned off and the mic1 signal is taken internally from the headphone output pin (39).
HPOUTR HPVOL
reg 04h UP: MONO HEADSET WITH MIC DOWN: STEREO HEADPHONE
RIGHT MIXER
LEFT MIXER HSDT
reg 5Ch
HPOUTL MIC
HEAD PHONE
OFF (hi-Z) '1'
L
R
MIC AMP
MS
reg 20h
'0'
MIC1
'0'
'1'
HPGND MIC2
HSEN
reg 5Ch
INTERNAL MIC
+ VMID
HSCP
reg 5Ch
HSDET
HSCMP
reg 5Ch
5mA
MPUEN
reg 5Ch
Figure 10 Headset Autodetect PD Rev 4.0 December 2003 17
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Production Data Figure 10 shows this function schematically. The output signal from the comparator is accessible by reading bit HSCP in register 5Ch. Auto detect may be used by setting HSEN bit, or external control by using the HSDT bit which is an over-ride that forces the headset tri-state and microphone path switching function to occur. This function would allow, for example, a stereo headphone to be used that had a microphone in the connecting lead, and a switch. The switch changes the headphone into a mono headset with microphone connected via the tip connection on the jack. If used in a product such as an MP3 capable phone it would allow the user to switch from headphone use to headset use by simply switching a single switch in the headphone cable, so at the same time answering or initiating telephone calls. It may also be possible to use the pull-up current to provide so called `phantom power' to dynamic microphones with appropriate choice of microphone.
DATA SLOT MAPPING
DAC data and SPDIF data sent to the device, ADC data sent from the device, can be optionally mapped into alternative slots under control of slot mapping bits located as follows: SLOT MAPPING DATA TYPE DAC data SPDIF data ADC data CONTROL BITS DSA[1,0] SPSA[1,0] ASS[1,0] REGISTER LOCATION 28h 2Ah 5Ch (non-AC'97 feature)
Table 4 Data Slot Mapping Control Default values and functional behavior are further described in the Serial Interface Register Map description. DAC slot mapping defaults are in Table 2.
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
A digital interface has been provided to control the WM9710 and transfer data to and from it. This serial interface is compatible with the Intel AC'97 specification. The main control interface functions are:
* * *
Control of analogue gain and signal paths through the mixer Bi-directional transfer of ADC and DAC words to and from AC'97 controller Selection of power-down modes
The WM9710 incorporates a 5-pin digital serial interface that links it to the AC'97 controller. AClink is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. With a minimum required DAC and ADC resolution of 16-bits, AC'97 may also be implemented with 18 or 20-bit DAC/ADC resolution, given the headroom that the AC-link architecture provides. The WM9710 provides support for 18bit audio operation.
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SLOT NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATAOUT
TAG CODEC ID
CMD ADR
CMD DATA
PCM LEFT
PCM RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD PCM L (n+1)
RSRVD PCM R (n+1)
RSRVD PCM C (n+1)
SDATAIN
TAG
STATUS ADDR
STATUS DATA
PCM LEFT
PCM RIGHT
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
SLOTREQ 3-12
DATA PHASE TAG PHASE
Figure 9 AC'97 Standard Bi-Directional Audio Frame
TAG PHASE
DATA PHASE 20.8S (48kHz)
SYNC
12.288MHz 81.4nS
BITCLK
SDATAOUT
VALID FRAME
SLOT(1)
SLOT(2)
SLOT(12)
'0'
'0'
'0'
19 SLOT (1)
0
19 SLOT (2)
0
19 SLOT (3)
0
19 SLOT (12)
0
END OF PREVIOUS AUDIO FRAME
TIME SLOT 'VALID' BITS ('1' = TIME SLOT CONTAINS VALID PCM DATA)
Figure 10 AC-link Audio Output Frame The datastreams currently defined by the AC'97 specification include: PCM playback - 2 output slots PCM record data - 2 input slots Control - 2 output slots Status - 2 input slots Optional modem line codec output 1 output slot Optional modem line codec input - 1 input slot Optional dedicated microphone input 1 input slot 2-channel composite PCM output stream 2-channel composite PCM input stream Control Register write port Control Register read port Modem line codec DAC input stream Modem line codec ADC output stream Dedicated microphone input stream in support of stereo AEC and/or other voice applications.
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Production Data Synchronisation of all AC-link data transactions is signalled by the WM9710 controller. The WM9710 drives the serial bit clock onto AC-link, which the AC'97 controller then qualifies with a synchronisation signal to construct audio frames. SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BITCLK). BITCLK, fixed at 12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The receiver of AC-link data, (WM9710 for outgoing data and AC'97 controller for incoming data), samples each serial bit on the falling edges of BITCLK. The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the data, (the WM9710 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0s during that slot's active time. SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that the WM9710 be implemented as a static design to allow its Register contents to remain intact when entering a power savings mode.
PLAY MASTER VOLUME REGISTERS (INDEX 02H, 04H AND 06H)
These registers manage the output signal volumes. Register 02h controls the stereo master volume (both right and left channels), Register 04h controls the stereo headphone out, and Register 06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at -dB. ML4 to ML0 is for left channel level, MR4 to MR0 is for the right channel and MM4 to MM0 is for the mono out channel. Support for the MSB of the volume level is not provided by the WM9710. If the MSB is written to, then the WM9710 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a 1xxxxx the WM9710 interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value written to it. The driver can use this feature to detect if support for the 6th bit is there or not. The default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000), which corresponds to 0dB gain with mute on. MUTE 0 0 0 1 MX4...MX0 0 0000 0 0001 1 1111 x xxxx FUNCTION 0dB attenuation 1.5dB attenuation 46.5dB attenuation
dB attenuation
Table 5 Volume Register Function The Headphone out has an additional 6dB boost, selectable by setting HPB in register 74h.
PC BEEP REGISTER (INDEX 0AH)
This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at -dB. WM9710 defaults to the PC-beep path being muted, so an external speaker should be provided within the PC to alert the user to power on self-test problems.
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MUTE 0 0 1 PV3...PV0 0000 1111 xxxx FUNCTION 0dB attenuation 45dB attenuation
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dB attenuation
Table 6 PC-beep Register Function
ANALOGUE MIXER INPUT GAIN REGISTERS (INDEX 0CH - 18H AND 72H)
This controls the gain/attenuation for each of the analogue inputs and mixer PGA. Each step corresponds to approximately 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at -dB. Note that the gain for the VID and AUX input channels is fixed at 0dB. Writes to the gain control bits for these channels are ignored, and the value of readback for these registers is always the default, with the exception of the mute bit 15 which may be written to and read from. The default value for the mono registers is 8008h, which corresponds to 0dB gain with mute on. The default value for stereo registers is 8808h, which corresponds to 0dB gain with mute on. MUTE 0 0 0 1 GX4...GX0 00000 01000 11111 xxxxx FUNCTION +12dB gain 0dB gain -34.5dB gain -dB gain
Table 7 Mixer Gain Control Register Function
REGISTER 0EH (MIC VOLUME REGISTER)
This has an extra bit that is for a 20dB boost. When bit 6 is set to 1 the 20dB boost is on. The default value is 8008h, which corresponds to 0dB gain with mute on.
RECORD SELECT CONTROL REGISTER (INDEX 1AH)
Used to select the record source independently for right and left (see Table 8). The default value is 0000h, which corresponds to Mic in. Setting Bit ADCNDAC in Register 5Ch selects a stereo mix WITHOUT DAC when (5 x 2 - 5 x 0) is 5. SR2 TO SR0 0 1 3 4 5 6 RIGHT RECORD SOURCE Mic CD in (R) Line in (R) Stereo mix (R) Mono mix Phone SL2 TO SL0 0 1 4 5 6 7 LEFT RECORD SOURCE Mic CD in (L) Line in (L) Stereo mix (L) Mono mix Phone
Table 8 Record Select Register Function
RECORD GAIN REGISTERS (INDEX 1CH)
1Ch sets the stereo input record gain with each step corresponding to 1.5dB. The MSB of the register is the mute bit. When this bit is set to 1, the level for both channels is set at -dB. The default value is 8000h, which corresponds to 0dB gain with mute on. MUTE 0 0 1 GX3...GX0 1111 0000 xxxxx FUNCTION +22.5dB gain 0dB gain -dB gain
Table 9 Record Gain Register Function
GENERAL PURPOSE REGISTER (INDEX 20H)
This register is used to control several miscellaneous functions of the WM9710.
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Production Data Below is a summary of each bit and its function. Only the POP, 3D, MIX, MS and LPBK bits are supported by the WM9710. The MS bit controls the Mic selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-link, allowing for full system performance measurements. The function default value is 0000h which is all off. BIT POP 3D MIX MS LPBK FUNCTION PCM out path and mute, 0 = pre-3D, 1 = post-3D 3D stereo enhancement on/off, 1 = on Mono output select 0 = Mix, 1 = Mic Mic select 0 = Mic1, 1 = Mic2 ADC/DAC loopback mode
3D CONTROL REGISTER (INDEX 22H)
This register is used to control the centre and/or depth of the 3D stereo enhancement function built into the AC'97 component. Only the depth bits DP0 to 3 have effect in the WM9710. DP3...DP0 0 1 8 15 Table 10 3D Control Register DEPTH 0%
Typical value 100%
POWERDOWN CONTROL/STATUS REGISTER (INDEX 26H)
This read/write register is used to program power-down states and monitor subsystem readiness. The lower half of this register is read only status, a 1 indicating that the subsection is ready. Ready is defined as the subsection able to perform in its nominal state. When this register is written the bit values that come in on AC-link will have no effect on read bits 0- 7. When the AC-link Codec Ready indicator bit (SDATAIN slot 0, bit 15) is a 1 it indicates that the AC-link and the WM9710 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any, are ready. Note that the normal default condition of WM9710 when RESETB is applied is `all active'. However, if pin 43 (PWRUP/LRC) is pulled `hi' during RESETB active, all PR bits are overridden and the device enters a low power mode. This allows a low power standby mode to be entered without writing to the device, a condition that is desirable for example, if batteries are changed in a PDA. The state of pin 43 is latched on the rising edge of RESETB and if the pin is `hi' then the WM9710 will remain in low power mode until register 26h is written to. READ BIT REF ANL DAC ADC FUNCTION VREFs up to nominal level Analogue mixers, etc ready DAC section ready to accept data ADC section ready to transmit data
Table 11 Powerdown Status Register Function The Powerdown modes are as follows. The first three bits are to be used individually rather than in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. PR0 and PR1 control the PCM ADCs and DACs only. PR6 powers down just the stereo Line Level output headphone amps on pins 39/41. The WM9710 also includes a low power DAC to headphone mode, whereby resetting PR1and PR6 enables the DAC and the path from the DAC to HPOUTL/R without having to power up the main mixer (PR2). The POP bit (reg 20h) also needs to be set for this mode. The headphone amplifier on the MONO output pin in not powered down by PR6, rather by PR2 or alternatively may be enabled by setting MONOEN in register 74h.
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WRITE BIT PR0 PR1 PR2 PR3 PR4 PR5 PR6 EAPD FUNCTION PCM in ADCs and input Mux Powerdown PCM out DACs Powerdown Analogue mixer Powerdown (VREF still on) Analogue mixer Powerdown (VREF off) Digital interface (AC-link) Powerdown (external clock off) Internal clock disable HP amp Powerdown External amplifier Powerdown
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Table 12 Powerdown Control Register Function
PR0 = 1
PR1 = 1
PR2 = 1
PR4 = 1
NORMAL
ADCs OFF PR0
DACs OFF PR1
ANALOGUE OFF PR2 OR PR3
DIGITAL I/F OFF PR4
SHUT OFF CODA LINK
PR0 = 0 AND ADC = 1
PR1 = 0 AND DAC = 1
PR2 = 0 AND ANL = 1
WARM RESET
READY = 1 DEFAULT
COLD RESET
Figure 11 An Example of the WM9710 Powerdown/Powerup Flow Figure 11 illustrates one example procedure to do a complete Powerdown of the WM9710. From normal operation sequential writes to the Powerdown Register are performed to Powerdown the WM9710 a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4) can be executed to shut down the WM9710's digital interface (AC-link). The part will remain in sleep mode with all its registers holding their static values. To wake up the WM9710, the AC'97 controller will send a pulse on the sync line issuing a warm reset. This will restart the WM9710's digital interface (resetting PR4 to 0). The WM9710 can also be woken up with a cold reset. A cold reset will cause a loss of values of the registers, as a cold reset will set them to their default states. When a section is powered back on, the Powerdown Control/Status Register (index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any operation that requires it.
PR0 = 1
PR1 = 1
PR4 = 1
NORMAL
ADC's OFF PR0
DACs OFF PR1
DIGITAL I/F OFF PR4
SHUT OFF CODA LINK
PR0 = 0 AND ADC = 1
PR1 = 0 AND DAC = 1
WARM RESET
Figure 12 The WM9710 Powerdown Flow with Analogue Still Active
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Production Data Figure 12 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This is used when the user could be playing a CD (or external LINEIN source) through WM9710 to the speakers but have most of the system in low power mode. The procedure for this follows the previous except that the analogue mixer is never shut down. Note that in order to go into ultimate low power mode, PR4 and PR5 are required to be set which turns off the oscillator circuit. Asserting SYNC resets the PR4 and PR5 bit and re-starts the oscillator in the same way as the AC link is restarted.
REGISTER 28H - EXTENDED AUDIO ID
The Extended Audio ID register is a read only register that identifies which extended audio features are supported (in addition to the original AC'97 features identified by reading the reset register at index 00h). A non zero value indicates the feature is supported. DATA BIT VRA DRA SPDIF VRM DSA0 DSA1 CDAC SDAC LDAC AMAP REV0 REV1 ID0 ID1 FUNCTION Variable rate audio support Double rate audio support SPDIF transmitter supported Variable rate Mic ADC support DAC slot mapping control DAC slot mapping control Centre DAC support Surround DAC support LFE DAC support Slot mapping support for Codec ID Revision number Revision number Codec configuration - pin 45 value Codec configuration - fixed in WM9710 VALUE 1 0 `1' = supported 0 See table below See table below 0 0 0 1 1 0 0 (Inverse of level at pin 45) 0
Table 13 Extended Audio ID Register DSA1, DSA0 00 01 10 11 DAC SLOT MAPPING Slots 3 & 4 Slots 7 & 8 Slots 6 & 9 Slots 10 & 11
Table 14 DAC Slot Mapping DAC slot mapping to slots 7 and 8 or slots 6 and 9 cannot be used in variable rate mode (VRA=1) for sample rates other than 48kHz.
REGISTER 2AH - EXTENDED AUDIO STATUS AND CONTROL REGISTER
The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. Note that SPDIF slot mapping default varies according to codec pin configuration. See Table 2. DATA BIT VRA SPDIF SPSA0 SPSA1 SPCV FUNCTION Enables variable rate audio mode SPDIF transmitter enable SPDIF slot assignment SPDIF slot assignment SPDIF validity bit READ/WRITE Read/write Read/write Read/write Read/write Read
Table 15 Extended Audio Status and Control Register
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SPSA0, SPSA1 00 01 10 11 SPDIF SLOT MAPPING Slots 3 & 4 Slots 7 & 8 Slots 6 & 9 Slots 10 & 11
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Table 16 SPDIF Slot Mapping
REGISTER 2Ch AND 32h - AUDIO SAMPLE RATE CONTROL REGISTERS
These registers are read/write registers that are written to, to select alternative sample rates for the audio PCM converters. Default is the 48kHz rate. Note that only Revision 2.2 recommended rates are supported by the WM9710, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read back. Sample rate is entered in binary form to the appropriate register.
REGISTERS 3AH - SPDIF CONTROL REGISTER
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or sub-frame in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in register 2Ah is `0'). Once the desired values have been written to this register, the contents should be read back to ensure that the sample rate in particular is supported, then SPDIF validity bit SPCV in register 2Ah should be read to ensure the desired configuration is valid. Only then should the SPDIF enable bit in register 2Ah be set. This ensures that control and status information start up correctly at the beginning of SPDIF transmission. WM9710 only supports an SPDIF sample rate of 48kHz. CONTROL BIT PRO AUDIB COPY PRE CC[6-0] L V FUNCTION Professional; `0' indicates consumer, `1' indicates professional Non-audio; `0' indicates data is PCM, `1' indicates non-PCM format (eg DD or DTS) Copyright; `0' indicates copyright is not asserted, `1' indicates copyright Pre-emphasis; `0' indicates not pre-emphasis, `1' indicates 50/15us pre-emphasis Category code; programmed as required by user Generation level; programmed as required by user Validity bit; `0' indicates frame valid, `1' indicates frame not valid
Table 17 SPDIF Control Register
VENDOR SPECIFIC REGISTERS (INDEX 5Ah - 7Ah)
These registers are vendor specific. Do not write to these registers unless the Vendor ID register has been checked first to ensure that the controller knows the source of the AC `97 component.
MIXER MUTE PATH (INDEX 5AH)
Bit 4 (MPM) is used to disable the path between the main input mixer and the lineout mixer. Setting this bit to 1, breaks the connection and allows the following combinations: DAC + PHONE + PCBEEP to line out / headphone out When writing to this register all bits (except MPM) must be written as a 0 or device function can not be guaranteed.
VENDOR SPECIFIC MODE CONTROL (INDEX 5CH)
Register 5Ch is a vendor specific control register used to control the function of non-AC'97 specified functions. This register defaults to all special features `disabled' i.e. All zeros.
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CONTROL BIT AMUTE HSCP MPUEN MHPZ PSEL HSDT HSEN HPND AMEN I 2S ADCNDAC ADCO HPF HSCMP ASS1 ASS0 FUNCTION
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Indicates automute has been detected in the audio DAC (all `0' data) - read only Headset detect comparator output - read only Mic pull up enable Mono headphone tristate enable PHONE to MONO path switch enable Overrides Headset detect comparator, forcing left headphone amp to tristate Headset auto-detect enable Headphone with no DAC enable Automute enable bit I2S data output enable ADC no DAC path enable ADC to SPDIF and/or I2S output ADC high pass filter disable; Headset comparator enable bit ADC slot map control ADC slot map control
Table 18 Vendor Specific Control Register 5Ch AMUTE indicates automute state has been detected. This is a read-only bit. 1 = automute detected. HSCP is a read only bit, indicating headset detected. It is the output from the headset autodetect comparator. 0 = headset detected. MPUEN enables a 5mA (typ) pull up current on the MIC1 input pin, which when a headset microphone of high impedance is plugged in, causes the MIC1 pin to pull up to above Vmid, and be detected. 1 = enable. MHPZ tristates the MONO headphone driver output buffer. 1 = tristate. PSEL enables the switch from PHONE input to MONO output; see block diagram. 1 = enable. HSDT overrides the headset auto-detect comparator, forcing the left headphone output to tristate and the HPLOUTL pin to be used as a headset microphone input path to the mic1 preamplifier input. 1 = autodetect comparator override. HSEN enables headset auto-detect function. HSCMP enables the headset detect comparator. 1 = enable. HPND enables the switch which outputs only the analog mixer output to the HPHONE outputs, without the DAC signal being summed in. See block diagram. 1 = enable. AMEN enables the DAC automute function, which detects zero data on both dac channels and auto-mutes the outputs under this condition. 1 = enable. Bit I2S enables I2S output, sending an LRCLK to pin 43 (PWRUP/LRC) and I2S data to the SPEN/I2S pin (pin 44). BITCLK is used to clock out the data. Only 48kHz data is supported. 1 = enable. ADCNDAC selects input to the ADC from before the point where the DAC signal is summed in. 1 = select. Bit ADCO is used to select data from the internal ADCs to be output as SPDIF or I S data on these pins rather than the data from the selected AC link slot. 1 = select. HPF turns off the digital high pass filter in the ADC output when set to `1'. ASS1, ASS0 are ADC slot mapping control bits. See table below. Default is slots 3 and 4.
2
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ASS1, ASS0 00 01 10 11 ADC SLOT MAPPING ( L/R) Slots 3 & 4 Slots 7 & 8 Slots 6 & 9 Slots 10 & 11
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Table 19 ADC Slot Mapping Control
VENDOR SPECIFIC GAIN CONTROL REGISTER (INDEX 72H)
This register controls the gain and mute functions applied to the mixer path. This PGA is not accommodated in the Intel specification, but is required in order to allow the option of simultaneous recording of the mixer output and playback of DAC signals. The function is as for the other mixer PGA's. However, the default value of the register is not-muted. If it is not used it will be transparent to the user. Normally this reigster would be used in collaboration with bit ADCNDAC in register 5Ch, allowing recording of the analog mix, manipulation in the digital domain by an external DSP, then playback through the DACs on the WM9710.
VENDOR SPECIFIC ADDITIONAL FUNCTIONALITY (INDEX 74H)
HPB boosts the headphone output by 6dB. 1 = 6dB boost enabled. I2S64 enables a 64fs bitclk output on SPDIF for i2s data output. 1 = enabled. MONOEN enables the mono output independently of PR2 (MIXER Powerdown). This allows the DAC to MONOUT path to be powered up by resetting PR1 and setting MONOEN while the Mixer is powered down (PR2 set), providing a lower power mode when the mixer function is not required.
VENDOR SPECIFIC ADDITIONAL FUNCTIONALITY (INDEX 78H)
The PHIZ bit in register 78h enables the PHONE and PCBEEP input pins. By default, these pins are disconnected from the audio mixer (PHIZ=0). All other bits in register 78h should be set to 0 at all times. When PHIZ=0, PHONE and PCBEEP are high impedance inputs. BIT PHIZ FUNCTION PHONE and PCBEEP input enable; 0 = disabled, 1 = enabled
VENDOR ID REGISTERS (INDEX 7CH & 7EH)
These registers are for specific vendor identification if so desired. The ID method is Microsoft's Plug and Play Vendor ID code. The first character of that ID is F7 to F0, the second character S7 to S0, and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the Vendor Revision number. In the WM9710 the vendor ID is set to WML5. Wolfson is a registered Microsoft Plug and Play vendor.
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SERIAL INTERFACE REGISTER MAP
The following table shows the function and address of the various control bits that are loaded and read through the serial interface. Reg 00h 02h 04h 06h Name Reset Master volume HPHONE volume Master volume mono PCBEEP volume Phone volume Mic volume Line in volume CD volume PCM out volume Rec select Rec gain General purpose 3D control Power/down control status Ext'd audio ID Ext'd audio stat/ctrl Audio DAC rate Audio ADC rate SPDIF control Mixer Path Mute Add. Function control Front mixer volume Add. Function Add. Function Vendor ID1 Vendor ID2 D15 X Mute Mute Mute D14 SE4 X X X D13 SE3 X X X D12 SE2 ML4 ML4 X D11 SE1 ML3 ML3 X D10 SE0 ML2 ML2 X D9 ID9 ML1 ML1 X D8 ID8 ML0 ML0 X D7 ID7 X X X D6 ID6 X X X D5 ID5 X X X D4 ID4 MR4 MR4 MM4 D3 ID3 MR3 MR3 MM3 D2 D1 ID2 ID1 MR2 MR1 MR2 MR1 MM2 MM1 D0 Default ID0 6150h MR0 8000h MR0 8000h MM0 8000h
0Ah 0Ch 0Eh 10h 12h 18h 1Ah 1Ch 20h 22h 26h 28h 2Ah 2Ch 32h 3Ah 5Ah 5Ch 72h 74h 78h 7Ch 7Eh
Mute Mute Mute Mute Mute Mute X Mute POP X APD ID1 X
X X X X X X X X X X PR6 ID0 X
X X X X X X X X 3D X PR5 X X
X X X GL4 GL4 GL4 X X X X PR4 X X
X X X GL3 GL3 GL3 X GL3 X X PR3
X X X GL2 GL2 GL2 SL2 GL2 X X PR2
X X X GL1 GL1 GL1 SL1 GL1 MIX X PR1
X X X GL0 GL0 GL0 SL0 GL0 MS X PR0
X X X X X 20dB X X X X X X X X X X LPBK X X X X X
X X X X X X X X X X X
PV3 GN4 GN4 GR4 GR4 GR4 X X X X X
PV2 GN3 GN3 GR3 GR3 GR3 X GR3 X DP3 REF
PV2 GN2 GN2 GR2 GR2 GR2 SR2 GR2 X DP2 ANL
PV0 GN1 GN1 GR1 GR1 GR1 SR1 GR1 X DP1 DAC
X GN0 GN0 GR0 GR0 GR0 SR0 GR0 X DP0 ADC VRA VRA
8000h 8008h 8008h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Fh 0605h 0000h BB80h BB80h 2000h 0000h 0000h 0808h
REV1 REV0 AMAP LDAC SDAC CDAC DSA1 DSA0 X SPCV X X X X SPSA1 SPSA0 SR11 SR10 SR9 SR8 SR11 SR10 SR9 SR8 L CC6 CC5 CC4 0 0 0 0 PSEL HSEN HSDT HPND GL3 X 0 F3 T3 GL2 X 0 F2 T2 GL1 X 0 F1 T1 GL0 X 0 F0 T0 SR7 SR6 SR7 SR6 CC3 CC2 0 0 AMEN I2S X X SR5 SR4 SR5 SR4 CC1 CC0 0 MPM ADCN ADCO DAC X GR4 X 0 S5 Rev5 X 0 S4 Rev4
VRM SPDIF DRA X SPDIF X SR3 SR3 PRE 0 HPF GR3 HPB 0 S3 Rev3 SR2 SR2 COPY 0 HS CMP GR2
SR15 SR14 SR15 SR14 V 0 0 0 AMUTE HSCP Mute X 0 F7 T7 X X 0 F6 T6
SR13 SR12 SR13 SR12 1 0 0 0 PUEN MHPZ X X 0 F5 T5 GL4 X 0 F4 T4
SR1 SR0 SR1 SR0 UDIB PRO 0 0 ASS1 ASS0 GR1 GR0
X X 0 PHIZ S7 S6 Rev7 Rev6
I2S64 X MONOEN 0000h 0 0 0 0000h S2 S1 S0 574Dh Rev2 Rev1 Rev0 4C05h
Table 20 Serial Interface Register Map Description Note: 1. Default values of register 28h and 2Ah depend on whether the device is a primary or secondary, and whether SPDIF capability is enabled by pulling pin 44 SPEN high. The conditions shown are for a primary codec with SPDIF capability. 2. When writing to register 5Ah all bits except MPM (bit 4) must be written as 0, otherwise device function can not be guaranteed.
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RECOMMENDED EXTERNAL COMPONENTS
DVDD AVDD 1
100nF
DVDD1 DVDD2 DGND1 DGND2 PWRUP/LRC VREF PCBEEP PHONE CDL CDGND CDR MIC1 MIC2 LINEINL LINEINR DNC DNC DNC DNC DNC DNC CID0 SDATAOUT BITCLK SDATAIN SYNC RESETB XTLIN HSDET EAPD SPDIF XTLOUT
24.576MHz XTAL 22pF 22pF
100nF
10uF
+ AGND HPGND 42 40
4 7
DGND DVDD
1uF 1uF
43 12 13 18 19 20 21 22 23 24 14 15 16 17 25 26
AGND 27 28
100nF 100nF 10uF
VREFOUT
100nF
9
AVDD
38
10uF
+
MIXER INPUTS
1uF 1uF 1uF 1uF 1uF 1uF 1uF
CAP2 CX3D1 CX3D2
32
100nF
+ 10uF
33 34
100nF
WM9710
DNC DNC DNC 29 30 31
47nF
AGND
AGND
LINEOUTL LINEOUTR MONOOUT HPOUTL
35 36 37 39 41
+ 2.2uF + 2.2uF + 2.2uF + 220uF + 220uF
STEREO OUTPUT MONO OUTPUT LINE LEVEL STEREO
AVDD
MASTER/ SLAVE SELECT
45 AVSS 5 6
HPOUTR
SPEN/I2S 44 46 47 48
AC-LINK
8 10 11
Notes: 1. All decoupling capacitors should be as close to WM9710 as possible. 2. AGND and DGND should be connected as close to WM9710 as possible.
2
3
DGND
Figure 13 External Components Diagram
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10uF
+
AGND
WM9710
Production Data
PACKAGE DIMENSIONS - TQFP
FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C
b
e
25
36
37
24
E1
E
48
13
1
12
c
D1 D
L
A A2
A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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PACKAGE DIMENSIONS - QFN
FL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH
D2 D2/2 37 48 L 36 1 INDEX AREA (D/2 X E/2)
DM029.C
SEE DETAIL 1
D
E2/2
E2 SEE DETAIL 2
E
25
12 2X b 2X aaa C aaa C
24 e
13
TOP VIEW
ccc C (A3) A 0.08 C
C
SEATING PLANE
A1
DETAIL 1
DETAIL 2
1
DETAIL 3
W T (A3) H b Exposed lead G 0.35mm 45 degrees
Datum
Terminal tip e/2
e R
Half etch tie bar
DETAIL 3
Symbols A A1 A3 b D D2 E E2 e G H L T W aaa bbb ccc REF
Dimensions (mm) NOM MAX 0.90 1.00 0.05 0.02 0.20 REF 0.18 0.25 0.30 7.00 BSC 5.00 5.15 5.25 7.00 BSC 5.00 5.15 5.25 0.5 BSC 0.213 0.1 0.50 0.30 0.4 0.1 0.2 Tolerances of Form and Position 0.15 0.10 0.10 MIN 0.80 0
NOTE
1
JEDEC, MO-220, VARIATION VKKD-2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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